1. Field of the Invention
This invention relates to a simplified method to calculate the numerical value of a polynomial function. Since many of the relations of scientific or industrial parameters given by mathematical formulae or numerical tables of empirical data can be represented with sufficient practical accuracy by polynomial expressions, this invention can be used in a broad field of scientific or industrial applications.
2. Description of the Prior Art
A function generator for polynomial functions comprising a cascade accumulator is described in my copending U.S. patent application Ser. No. 505,849 under amended title "Digital Function Generator Utilizing Cascade Accumulation", filed on Sept. 13, 1974.
FIG. 1 is a schematic block diagram of a cascade arrangement of memories M0, M1, M2, . . . Mn for illustrating the general principle of cascade accumulation, and FIG. 2 shows an illustrative form of cascade accumulator as shown in FIG. 8 of the above patent application Ser. No. 505,849, representing an embodiment of what is termed a second kind of cascade accumulator, as described in the specification of the above patent application. In the illustrative FIG. 2 embodiment, memories M0 to M4 are arranged in a shift register configuration, along with a delay circuit D and an adder A. Although only five memories M are shown for simplifying this explanation, (n+1) memories M may be employed.
To obtain the value of the function w expressed by equation: EQU w = a.sub.0 + a.sub.1 x + a.sub.2 x.sup.2 + . . . + a.sub.n x.sup.n ( 1)
where:
w is the function, the value of which is to be obtained, PA1 a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.n are constants, PA1 x is the independent variable, and PA1 n is an integer and n.gtoreq.2,
And for the simplified case of FIG. 2 where n = 4, the initial values to be loaded in the memories M0, M1, M2, M3 and M4 are given respectively by: EQU a'.sub.0 = a.sub.0 ( 2) EQU a'.sub.1 = a.sub.1 + a.sub.2 + a.sub.3 + a.sub.4 ( 3) EQU a'.sub.2 = 2a.sub.2 + 6a.sub.3 + 14a.sub.4 ( 4) EQU a'.sub.3 = 6a.sub.3 + 36a.sub.4 ( 5) EQU a'.sub.4 = 24a.sub.4 ( 6)
As shown by FIG. 2, the memories M0, M1, . . . , M4 storing the values a'.sub.0, a'.sub.1 , . . . , a'.sub.4 respectively as their initial values at x=0, are arranged in series to form a shift register. This shift register is read out and its output digits are supplied to a first input of the adder A and also to the input of a delay circuit D which delays the signals passing through it by an amount equivalent to the number of bits of each of the memories M0, M1, . . . , M4. The output from the delay circuit D is supplied to the other input of the adder A. The output from the adder A is rewritten in the shift register formed by the memories M0, M1, . . . , M4. By reading out the shift register contents and rewriting those contents back into the shift register once, one cycle of cascade additions is performed; by performing x cycles of this operation, the value of the function w is obtained in the memory M0. This prior art arrangement simplifies the construction of a function generator through the utilization of the technique of cascade accumulation, and serves to economize (i.e., reduce the cost of) the apparatus and improve its realibility as well.